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SNVS570L – JANUARY 2009 – REVISED MAY 2013
ANGLE DETECT
The Angle Detect circuit uses a comparator with a fixed threshold voltage of 7.21V to monitor the BLDR pin to
determine whether the triac is on or off. The output of the comparator drives the ASNS buffer and also controls
the Bleeder circuit. A 4 μs delay line on the output is used to filter out noise that could be present on this signal.
The output of the Angle Detect circuit is limited to a 0V to 4.0V swing by the buffer and presented to the ASNS
pin. R1 and C3 comprise a low-pass filter with a bandwidth on the order of 1.0Hz.
The Angle Detect circuit and its filter produce a DC level which corresponds to the duty cycle (relative on-time) of
the triac dimmer. As a result, the LM3445 will work equally well with 50Hz or 60Hz line voltages.
BLEEDER
While the BLDR pin is below the 7.21V threshold, the bleeder MOSFET is on to place a small load (230 ? ) on the
series pass regulator. This additional load is necessary to complete the circuit through the triac dimmer so that
the dimmer delay circuit can operate correctly. Above 7.21V, the bleeder resistor is removed to increase
efficiency.
FLTR1 PIN
The FLTR1 pin has two functions. Normally, it is fed by ASNS through filter components R1 and C3 and drives
the dim decoder. However, if the FLTR1 pin is tied above 4.9V (typical), e.g., to VCC, the Ramp Comparator is
DIM DECODER
The ramp generator produces a 5.85 kHz saw tooth wave with a minimum of 1.0V and a maximum of 3.0V. The
filtered ASNS signal enters pin FLTR1 where it is compared against the output of the Ramp Generator.
The output of the ramp comparator will have an on-time which is inversely proportional to the average voltage
level at pin FLTR1. However, since the FLTR1 signal can vary between 0V and 4.0V (the limits of the ASNS pin),
and the Ramp Generator signal only varies between 1.0V and 3.0V, the output of the ramp comparator will be on
continuously for V FLTR1 < 1.0V and off continuously for V FLTR1 > 3.0V. This allows a decoding range from 45° to
135° to provide a 0 – 100% dimming range.
The output of the ramp comparator drives both a common-source N-channel MOSFET through a Schmitt trigger
and the DIM pin (see MASTER/SLAVE OPERATION for further functions of the DIM pin). The MOSFET drain is
pulled up to 750 mV by a 50 k ? resistor.
Since the MOSFET inverts the output of the ramp comparator, the drain voltage of the MOSFET is proportional
to the duty cycle of the line voltage that comes through the triac dimmer. The amplitude of the ramp generator
causes this proportionality to "hard limit" for duty cycles above 75% and below 25%.
The MOSFET drain signal next passes through an RC filter comprised of an internal 370 k ? resistor, and an
external capacitor on pin FLTR2. This forms a second low pass filter to further reduce the ripple in this signal,
which is used as a reference by the PWM comparator. This RC filter is generally set to 10Hz.
The net effect is that the output of the dim decoder is a DC voltage whose amplitude varies from near 0V to 750
mV as the duty cycle of the dimmer varies from 25% to 75%. This corresponds to conduction angles of 45° to
135°, respectively.
The output voltage of the Dim Decoder directly controls the peak current that will be delivered by Q2 during its
on-time. See BUCK CONVERTER for details.
As the triac fires beyond 135°, the DIM decoder no longer controls the dimming. At this point the LEDs will dim
gradually for one of two reasons:
1. The voltage at V BUCK decreases and the buck converter runs out of headroom and causes LED current to
decrease as V BUCK decreases.
2. Minimum on-time is reached which fixes the duty-cycle and therefore reduces the voltage at V BUCK .
The transition from dimming with the DIM decoder to headroom or minimum on-time dimming is seamless. LED
currents from full load to as low as 0.5 mA can be easily achieved.
12
Product Folder Links: LM3445
Copyright ? 2009–2013, Texas Instruments Incorporated
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